
`timescale 1 ps / 1 ps

module Soc_xlnx(
    ddr4_sdram_c1_083_act_n,
    ddr4_sdram_c1_083_adr,
    ddr4_sdram_c1_083_ba,
    ddr4_sdram_c1_083_bg,
    ddr4_sdram_c1_083_ck_c,
    ddr4_sdram_c1_083_ck_t,
    ddr4_sdram_c1_083_cke,
    ddr4_sdram_c1_083_cs_n,
    ddr4_sdram_c1_083_dm_n,
    ddr4_sdram_c1_083_dq,
    ddr4_sdram_c1_083_dqs_c,
    ddr4_sdram_c1_083_dqs_t,
    ddr4_sdram_c1_083_odt,
    ddr4_sdram_c1_083_reset_n,
    default_250mhz_clk1_clk_n,
    default_250mhz_clk1_clk_p,
    reset,
    spi_flash_io0_io,
    spi_flash_io1_io,
    spi_flash_io2_io,
    spi_flash_io3_io,
    spi_flash_ss_io,
    rs232_uart_rxd,
    rs232_uart_txd
    );

output          ddr4_sdram_c1_083_act_n;
output [16:0]   ddr4_sdram_c1_083_adr;
output [1:0]    ddr4_sdram_c1_083_ba;
output          ddr4_sdram_c1_083_bg;
output          ddr4_sdram_c1_083_ck_c;
output          ddr4_sdram_c1_083_ck_t;
output          ddr4_sdram_c1_083_cke;
output          ddr4_sdram_c1_083_cs_n;
inout [7:0]     ddr4_sdram_c1_083_dm_n;
inout [63:0]    ddr4_sdram_c1_083_dq;
inout [7:0]     ddr4_sdram_c1_083_dqs_c;
inout [7:0]     ddr4_sdram_c1_083_dqs_t;
output          ddr4_sdram_c1_083_odt;
output          ddr4_sdram_c1_083_reset_n;
input           default_250mhz_clk1_clk_n;
input           default_250mhz_clk1_clk_p;
input           reset;
input           rs232_uart_rxd;
output          rs232_uart_txd;
inout           spi_flash_io0_io;
inout           spi_flash_io1_io;
inout           spi_flash_io2_io;
inout           spi_flash_io3_io;
inout           spi_flash_ss_io;

// parameter
parameter int unsigned AXI_ID_WIDTH      = 9;
parameter int unsigned AXI_ADDR_WIDTH    = 48;
parameter int unsigned AXI_DATA_WIDTH    = 128;
parameter int unsigned AXI_USER_WIDTH    = 2;

// declaration wire

wire            clk_100M;
wire            clk_10M;
wire            core_reset;
wire            peripheral_aresetn;
wire            ddr4_sdram_c1_083_act_n;
wire [16:0]     ddr4_sdram_c1_083_adr;
wire [1:0]      ddr4_sdram_c1_083_ba;
wire            ddr4_sdram_c1_083_bg;
wire            ddr4_sdram_c1_083_ck_c;
wire            ddr4_sdram_c1_083_ck_t;
wire            ddr4_sdram_c1_083_cke;
wire            ddr4_sdram_c1_083_cs_n;
wire [7:0]      ddr4_sdram_c1_083_dm_n;
wire [63:0]     ddr4_sdram_c1_083_dq;
wire [7:0]      ddr4_sdram_c1_083_dqs_c;
wire [7:0]      ddr4_sdram_c1_083_dqs_t;
wire            ddr4_sdram_c1_083_odt;
wire            ddr4_sdram_c1_083_reset_n;
wire            default_250mhz_clk1_clk_n;
wire            default_250mhz_clk1_clk_p;
wire            reset;
wire            rs232_uart_rxd;
wire            rs232_uart_txd;


wire [47:0]     s_axi_araddr;
wire [1:0]      s_axi_arburst;
wire [3:0]      s_axi_arcache;
wire [AXI_ID_WIDTH-1:0]      s_axi_arid;
wire [7:0]      s_axi_arlen;
wire [0:0]      s_axi_arlock;
wire [2:0]      s_axi_arprot;
wire [3:0]      s_axi_arqos;
wire            s_axi_arready;
wire [3:0]      s_axi_arregion;
wire [2:0]      s_axi_arsize;
wire            s_axi_arvalid;
wire [47:0]     s_axi_awaddr;
wire [1:0]      s_axi_awburst;
wire [3:0]      s_axi_awcache;
wire [AXI_ID_WIDTH-1:0]      s_axi_awid;
wire [7:0]      s_axi_awlen;
wire [0:0]      s_axi_awlock;
wire [2:0]      s_axi_awprot;
wire [3:0]      s_axi_awqos;
wire            s_axi_awready;
wire [3:0]      s_axi_awregion;
wire [2:0]      s_axi_awsize;
wire            s_axi_awvalid;
wire [AXI_ID_WIDTH-1:0]      s_axi_bid;
wire            s_axi_bready;
wire [1:0]      s_axi_bresp;
wire            s_axi_bvalid;
wire [127:0]    s_axi_rdata;
wire [AXI_ID_WIDTH-1:0]      s_axi_rid;
wire            s_axi_rlast;
wire            s_axi_rready;
wire [1:0]      s_axi_rresp;
wire            s_axi_rvalid;
wire [127:0]    s_axi_wdata;
wire            s_axi_wlast;
wire            s_axi_wready;
wire [15:0]     s_axi_wstrb;
wire            s_axi_wvalid;


wire   [1:0]    core_in_core_id;
wire   [7:0]    core_in_interrupt;
wire            core_in_ipi;
wire            uart_int;

assign core_in_core_id = {1'b0, 1'b0};
assign core_in_interrupt = {1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, uart_int};
assign core_in_ipi = 1'b0;


Top core (
   .io_axi_aw_valid         (s_axi_awvalid             ), //o
   .io_axi_aw_ready         (s_axi_awready             ), //i
   .io_axi_aw_payload_addr  (s_axi_awaddr[47:0]        ), //o
   .io_axi_aw_payload_id    (s_axi_awid[AXI_ID_WIDTH-1:0]           ), //o
   .io_axi_aw_payload_len   (s_axi_awlen[7:0]          ), //o
   .io_axi_aw_payload_size  (s_axi_awsize[2:0]         ), //o
   .io_axi_aw_payload_burst (s_axi_awburst[1:0]        ), //o
   .io_axi_aw_payload_cache (s_axi_awcache[3:0]        ), //o
   .io_axi_aw_payload_prot  (s_axi_awprot[2:0]         ), //o
   
   .io_axi_w_valid          (s_axi_wvalid              ), //o
   .io_axi_w_ready          (s_axi_wready              ), //i
   .io_axi_w_payload_data   (s_axi_wdata[127:0]        ), //o
   .io_axi_w_payload_strb   (s_axi_wstrb[15:0]         ), //o
   .io_axi_w_payload_last   (s_axi_wlast               ), //o
   
   .io_axi_b_valid          (s_axi_bvalid              ), //i
   .io_axi_b_ready          (s_axi_bready              ), //o
   .io_axi_b_payload_id     (s_axi_bid[AXI_ID_WIDTH-1:0]            ), //i
   .io_axi_b_payload_resp   (s_axi_bresp               ), //i
   
   .io_axi_ar_valid         (s_axi_arvalid             ), //o
   .io_axi_ar_ready         (s_axi_arready             ), //i
   .io_axi_ar_payload_addr  (s_axi_araddr[47:0]        ), //o
   .io_axi_ar_payload_id    (s_axi_arid[AXI_ID_WIDTH-1:0]           ), //o
   .io_axi_ar_payload_len   (s_axi_arlen[7:0]          ), //o
   .io_axi_ar_payload_size  (s_axi_arsize[2:0]         ), //o
   .io_axi_ar_payload_burst (s_axi_arburst[1:0]        ), //o
   .io_axi_ar_payload_cache (s_axi_arcache[3:0]        ), //o
   .io_axi_ar_payload_prot  (s_axi_arprot[2:0]         ), //o    
   
   .io_axi_r_valid          (s_axi_rvalid              ), //i
   .io_axi_r_ready          (s_axi_rready              ), //o
   .io_axi_r_payload_data   (s_axi_rdata[127:0]        ), //i
   .io_axi_r_payload_id     (s_axi_rid[AXI_ID_WIDTH-1:0]            ), //i
   .io_axi_r_payload_last   (s_axi_rlast               ), //i  
   .io_axi_r_payload_resp   (s_axi_rresp               ), //i   
   
   // .io_core_in_core_id      (core_in_core_id[1:0]      ), //i
   .io_core_in_interrupt    (core_in_interrupt[7:0]    ), //i
   // .io_core_in_ipi          (core_in_ipi               ), //i    
   
   .io_soft_fpu_0_value     (128'h0                    ), //i
   .io_soft_fpu_0_vzoui     (5'h0                      ), //i
   .io_soft_fpu_1_value     (128'h0                    ), //i
   .io_soft_fpu_1_vzoui     (5'h0                      ), //i
   .io_soft_fpu_2_value     (128'h0                    ), //i
   .io_soft_fpu_2_vzoui     (5'h0                      ), //i
   .io_soft_fpu_3_value     (128'h0                    ), //i
   .io_soft_fpu_3_vzoui     (5'h0                      ), //i
   .reset                   (core_reset                ), //i
   .clk                     (clk_10M                   ), //i

   // unused output port
   .io_soft_fpu_0_info_a            (),
   .io_soft_fpu_0_info_b            (),
   .io_soft_fpu_0_info_c            (),
   .io_soft_fpu_0_info_cat          (),
   .io_soft_fpu_0_info_op           (),
   .io_soft_fpu_0_info_size         (),
   .io_soft_fpu_0_info_prf          (),
   .io_soft_fpu_0_info_rob          (),
   .io_soft_fpu_0_info_brq          (),
   .io_soft_fpu_0_info_fcc          (),
   .io_soft_fpu_0_info_rm           (),
   .io_soft_fpu_0_info_latency      (),
   .io_soft_fpu_0_info_write_type   (),
   .io_soft_fpu_0_valid             (),
   .io_soft_fpu_1_info_a            (),
   .io_soft_fpu_1_info_b            (),
   .io_soft_fpu_1_info_c            (),
   .io_soft_fpu_1_info_cat          (),
   .io_soft_fpu_1_info_op           (),
   .io_soft_fpu_1_info_size         (),
   .io_soft_fpu_1_info_prf          (),
   .io_soft_fpu_1_info_rob          (),
   .io_soft_fpu_1_info_brq          (),
   .io_soft_fpu_1_info_fcc          (),
   .io_soft_fpu_1_info_rm           (),
   .io_soft_fpu_1_info_latency      (),
   .io_soft_fpu_1_info_write_type   (),
   .io_soft_fpu_1_valid             (),
   .io_soft_fpu_2_info_a            (),
   .io_soft_fpu_2_info_b            (),
   .io_soft_fpu_2_info_c            (),
   .io_soft_fpu_2_info_cat          (),
   .io_soft_fpu_2_info_op           (),
   .io_soft_fpu_2_info_size         (),
   .io_soft_fpu_2_info_prf          (),
   .io_soft_fpu_2_info_rob          (),
   .io_soft_fpu_2_info_brq          (),
   .io_soft_fpu_2_info_fcc          (),
   .io_soft_fpu_2_info_rm           (),
   .io_soft_fpu_2_info_latency      (),
   .io_soft_fpu_2_info_write_type   (),
   .io_soft_fpu_2_valid             (),
   .io_soft_fpu_3_info_a            (),
   .io_soft_fpu_3_info_b            (),
   .io_soft_fpu_3_info_c            (),
   .io_soft_fpu_3_info_cat          (),
   .io_soft_fpu_3_info_op           (),
   .io_soft_fpu_3_info_size         (),
   .io_soft_fpu_3_info_prf          (),
   .io_soft_fpu_3_info_rob          (),
   .io_soft_fpu_3_info_brq          (),
   .io_soft_fpu_3_info_fcc          (),
   .io_soft_fpu_3_info_rm           (),
   .io_soft_fpu_3_info_latency      (),
   .io_soft_fpu_3_info_write_type   (),
   .io_soft_fpu_3_valid             ()
  );


assign  s_axi_awlock = '0;
assign  s_axi_awqos = '0;
assign  s_axi_awregion = '0;

assign  s_axi_arlock = '0;
assign  s_axi_arqos = '0;
assign  s_axi_arregion = '0;

// UNUSED!
// s_axi_bresp;
// s_axi_rresp;


wire [47:0]     bd_axi_araddr;
wire [1:0]      bd_axi_arburst;
wire [3:0]      bd_axi_arcache;
wire [AXI_ID_WIDTH-1:0]      bd_axi_arid;
wire [7:0]      bd_axi_arlen;
wire [0:0]      bd_axi_arlock;
wire [2:0]      bd_axi_arprot;
wire [3:0]      bd_axi_arqos;
wire            bd_axi_arready;
wire [3:0]      bd_axi_arregion;
wire [2:0]      bd_axi_arsize;
wire            bd_axi_arvalid;
wire [47:0]     bd_axi_awaddr;
wire [1:0]      bd_axi_awburst;
wire [3:0]      bd_axi_awcache;
wire [AXI_ID_WIDTH-1:0]      bd_axi_awid;
wire [7:0]      bd_axi_awlen;
wire [0:0]      bd_axi_awlock;
wire [2:0]      bd_axi_awprot;
wire [3:0]      bd_axi_awqos;
wire            bd_axi_awready;
wire [3:0]      bd_axi_awregion;
wire [2:0]      bd_axi_awsize;
wire            bd_axi_awvalid;
wire [AXI_ID_WIDTH-1:0]      bd_axi_bid;
wire            bd_axi_bready;
wire [1:0]      bd_axi_bresp;
wire            bd_axi_bvalid;
wire [127:0]    bd_axi_rdata;
wire [AXI_ID_WIDTH-1:0]      bd_axi_rid;
wire            bd_axi_rlast;
wire            bd_axi_rready;
wire [1:0]      bd_axi_rresp;
wire            bd_axi_rvalid;
wire [127:0]    bd_axi_wdata;
wire            bd_axi_wlast;
wire            bd_axi_wready;
wire [15:0]     bd_axi_wstrb;
wire            bd_axi_wvalid;


xlnx_clock_converter clock_converter (
  .s_axi_aclk        (clk_10M),                        // input wire s_axi_aclk
  .s_axi_aresetn     (peripheral_aresetn),             // input wire s_axi_aresetn
  .s_axi_awid        (s_axi_awid),                     // input wire [4 : 0] s_axi_awid
  .s_axi_awaddr      (s_axi_awaddr),                   // input wire [47 : 0] s_axi_awaddr
  .s_axi_awlen       (s_axi_awlen),                    // input wire [7 : 0] s_axi_awlen
  .s_axi_awsize      (s_axi_awsize),                   // input wire [2 : 0] s_axi_awsize
  .s_axi_awburst     (s_axi_awburst),                  // input wire [1 : 0] s_axi_awburst
  .s_axi_awlock      (s_axi_awlock),                   // input wire [0 : 0] s_axi_awlock
  .s_axi_awcache     (s_axi_awcache),                  // input wire [3 : 0] s_axi_awcache
  .s_axi_awprot      (s_axi_awprot),                   // input wire [2 : 0] s_axi_awprot
  .s_axi_awregion    (s_axi_awregion),                 // input wire [3 : 0] s_axi_awregion
  .s_axi_awqos       (s_axi_awqos),                    // input wire [3 : 0] s_axi_awqos
  .s_axi_awvalid     (s_axi_awvalid),                  // input wire s_axi_awvalid
  .s_axi_awready     (s_axi_awready),                  // output wire s_axi_awready
  .s_axi_wdata       (s_axi_wdata),                    // input wire [127 : 0] s_axi_wdata
  .s_axi_wstrb       (s_axi_wstrb),                    // input wire [63 : 0] s_axi_wstrb
  .s_axi_wlast       (s_axi_wlast),                    // input wire s_axi_wlast
  .s_axi_wvalid      (s_axi_wvalid),                   // input wire s_axi_wvalid
  .s_axi_wready      (s_axi_wready),                   // output wire s_axi_wready
  .s_axi_bid         (s_axi_bid),                      // output wire [4 : 0] s_axi_bid
  .s_axi_bresp       (s_axi_bresp),                    // output wire [1 : 0] s_axi_bresp
  .s_axi_bvalid      (s_axi_bvalid),                   // output wire s_axi_bvalid
  .s_axi_bready      (s_axi_bready),                   // input wire s_axi_bready
  .s_axi_arid        (s_axi_arid),                     // input wire [4 : 0] s_axi_arid
  .s_axi_araddr      (s_axi_araddr),                   // input wire [47 : 0] s_axi_araddr
  .s_axi_arlen       (s_axi_arlen),                    // input wire [7 : 0] s_axi_arlen
  .s_axi_arsize      (s_axi_arsize),                   // input wire [2 : 0] s_axi_arsize
  .s_axi_arburst     (s_axi_arburst),                  // input wire [1 : 0] s_axi_arburst
  .s_axi_arlock      (s_axi_arlock),                   // input wire [0 : 0] s_axi_arlock
  .s_axi_arcache     (s_axi_arcache),                  // input wire [3 : 0] s_axi_arcache
  .s_axi_arprot      (s_axi_arprot),                   // input wire [2 : 0] s_axi_arprot
  .s_axi_arregion    (s_axi_arregion),                 // input wire [3 : 0] s_axi_arregion
  .s_axi_arqos       (s_axi_arqos),                    // input wire [3 : 0] s_axi_arqos
  .s_axi_arvalid     (s_axi_arvalid),                  // input wire s_axi_arvalid
  .s_axi_arready     (s_axi_arready),                  // output wire s_axi_arready
  .s_axi_rid         (s_axi_rid),                      // output wire [4 : 0] s_axi_rid
  .s_axi_rdata       (s_axi_rdata),                    // output wire [127 : 0] s_axi_rdata
  .s_axi_rresp       (s_axi_rresp),                    // output wire [1 : 0] s_axi_rresp
  .s_axi_rlast       (s_axi_rlast),                    // output wire s_axi_rlast
  .s_axi_rvalid      (s_axi_rvalid),                   // output wire s_axi_rvalid
  .s_axi_rready      (s_axi_rready),                   // input wire s_axi_rready
  
  .m_axi_aclk        (clk_100M),                       // input wire m_axi_aclk
  .m_axi_aresetn     (peripheral_aresetn),             // input wire m_axi_aresetn
  .m_axi_awid        (bd_axi_awid),                    // output wire [4 : 0] m_axi_awid
  .m_axi_awaddr      (bd_axi_awaddr),                  // output wire [47 : 0] m_axi_awaddr
  .m_axi_awlen       (bd_axi_awlen),                   // output wire [7 : 0] m_axi_awlen
  .m_axi_awsize      (bd_axi_awsize),                  // output wire [2 : 0] m_axi_awsize
  .m_axi_awburst     (bd_axi_awburst),                 // output wire [1 : 0] m_axi_awburst
  .m_axi_awlock      (bd_axi_awlock),                  // output wire [0 : 0] m_axi_awlock
  .m_axi_awcache     (bd_axi_awcache),                 // output wire [3 : 0] m_axi_awcache
  .m_axi_awprot      (bd_axi_awprot),                  // output wire [2 : 0] m_axi_awprot
  .m_axi_awregion    (bd_axi_awregion),                // output wire [3 : 0] m_axi_awregion
  .m_axi_awqos       (bd_axi_awqos),                   // output wire [3 : 0] m_axi_awqos
  .m_axi_awvalid     (bd_axi_awvalid),                 // output wire m_axi_awvalid
  .m_axi_awready     (bd_axi_awready),                 // input wire m_axi_awready
  .m_axi_wdata       (bd_axi_wdata),                   // output wire [127 : 0] m_axi_wdata
  .m_axi_wstrb       (bd_axi_wstrb),                   // output wire [63 : 0] m_axi_wstrb
  .m_axi_wlast       (bd_axi_wlast),                   // output wire m_axi_wlast
  .m_axi_wvalid      (bd_axi_wvalid),                  // output wire m_axi_wvalid
  .m_axi_wready      (bd_axi_wready),                  // input wire m_axi_wready
  .m_axi_bid         (bd_axi_bid),                     // input wire [4 : 0] m_axi_bid
  .m_axi_bresp       (bd_axi_bresp),                   // input wire [1 : 0] m_axi_bresp
  .m_axi_bvalid      (bd_axi_bvalid),                  // input wire m_axi_bvalid
  .m_axi_bready      (bd_axi_bready),                  // output wire m_axi_bready
  .m_axi_arid        (bd_axi_arid),                    // output wire [4 : 0] m_axi_arid
  .m_axi_araddr      (bd_axi_araddr),                  // output wire [47 : 0] m_axi_araddr
  .m_axi_arlen       (bd_axi_arlen),                   // output wire [7 : 0] m_axi_arlen
  .m_axi_arsize      (bd_axi_arsize),                  // output wire [2 : 0] m_axi_arsize
  .m_axi_arburst     (bd_axi_arburst),                 // output wire [1 : 0] m_axi_arburst
  .m_axi_arlock      (bd_axi_arlock),                  // output wire [0 : 0] m_axi_arlock
  .m_axi_arcache     (bd_axi_arcache),                 // output wire [3 : 0] m_axi_arcache
  .m_axi_arprot      (bd_axi_arprot),                  // output wire [2 : 0] m_axi_arprot
  .m_axi_arregion    (bd_axi_arregion),                // output wire [3 : 0] m_axi_arregion
  .m_axi_arqos       (bd_axi_arqos),                   // output wire [3 : 0] m_axi_arqos
  .m_axi_arvalid     (bd_axi_arvalid),                 // output wire m_axi_arvalid
  .m_axi_arready     (bd_axi_arready),                 // input wire m_axi_arready
  .m_axi_rid         (bd_axi_rid),                     // input wire [4 : 0] m_axi_rid
  .m_axi_rdata       (bd_axi_rdata),                   // input wire [127 : 0] m_axi_rdata
  .m_axi_rresp       (bd_axi_rresp),                   // input wire [1 : 0] m_axi_rresp
  .m_axi_rlast       (bd_axi_rlast),                   // input wire m_axi_rlast
  .m_axi_rvalid      (bd_axi_rvalid),                  // input wire m_axi_rvalid
  .m_axi_rready      (bd_axi_rready)                   // output wire m_axi_rready
);


xlnx_bd_soc_wrapper bd_soc (
   .ddr4_sdram_c1_083_act_n      (ddr4_sdram_c1_083_act_n),
   .ddr4_sdram_c1_083_adr        (ddr4_sdram_c1_083_adr),
   .ddr4_sdram_c1_083_ba         (ddr4_sdram_c1_083_ba),
   .ddr4_sdram_c1_083_bg         (ddr4_sdram_c1_083_bg),
   .ddr4_sdram_c1_083_ck_c       (ddr4_sdram_c1_083_ck_c),
   .ddr4_sdram_c1_083_ck_t       (ddr4_sdram_c1_083_ck_t),
   .ddr4_sdram_c1_083_cke        (ddr4_sdram_c1_083_cke),
   .ddr4_sdram_c1_083_cs_n       (ddr4_sdram_c1_083_cs_n),
   .ddr4_sdram_c1_083_dm_n       (ddr4_sdram_c1_083_dm_n),
   .ddr4_sdram_c1_083_dq         (ddr4_sdram_c1_083_dq),
   .ddr4_sdram_c1_083_dqs_c      (ddr4_sdram_c1_083_dqs_c),
   .ddr4_sdram_c1_083_dqs_t      (ddr4_sdram_c1_083_dqs_t),
   .ddr4_sdram_c1_083_odt        (ddr4_sdram_c1_083_odt),
   .ddr4_sdram_c1_083_reset_n    (ddr4_sdram_c1_083_reset_n),
   .default_250mhz_clk1_clk_n    (default_250mhz_clk1_clk_n),
   .default_250mhz_clk1_clk_p    (default_250mhz_clk1_clk_p),
   .rs232_uart_rxd               (rs232_uart_rxd),
   .rs232_uart_txd               (rs232_uart_txd),
   .spi_flash_io0_io             (spi_flash_io0_io),
   .spi_flash_io1_io             (spi_flash_io1_io),
   .spi_flash_io2_io             (spi_flash_io2_io),
   .spi_flash_io3_io             (spi_flash_io3_io),
   .spi_flash_ss_io              (spi_flash_ss_io),
   .reset                        (reset),

   .clk_10M                      (clk_10M),
   .clk_100M                     (clk_100M),
   .core_reset                   (core_reset),
   .peripheral_aresetn           (peripheral_aresetn),

   // AXI 
   .s_axi_araddr                 (bd_axi_araddr),
   .s_axi_arburst                (bd_axi_arburst),
   .s_axi_arcache                (bd_axi_arcache),
   .s_axi_arid                   (bd_axi_arid),
   .s_axi_arlen                  (bd_axi_arlen),
   .s_axi_arlock                 (bd_axi_arlock),
   .s_axi_arprot                 (bd_axi_arprot),
   .s_axi_arqos                  (bd_axi_arqos),
   .s_axi_arready                (bd_axi_arready),
   // .s_axi_arregion               (bd_axi_arregion),
   .s_axi_arsize                 (bd_axi_arsize),
   .s_axi_arvalid                (bd_axi_arvalid),
   .s_axi_awaddr                 (bd_axi_awaddr),
   .s_axi_awburst                (bd_axi_awburst),
   .s_axi_awcache                (bd_axi_awcache),
   .s_axi_awid                   (bd_axi_awid),
   .s_axi_awlen                  (bd_axi_awlen),
   .s_axi_awlock                 (bd_axi_awlock),
   .s_axi_awprot                 (bd_axi_awprot),
   .s_axi_awqos                  (bd_axi_awqos),
   .s_axi_awready                (bd_axi_awready),
   // .s_axi_awregion               (bd_axi_awregion),
   .s_axi_awsize                 (bd_axi_awsize),
   .s_axi_awvalid                (bd_axi_awvalid),
   .s_axi_bid                    (bd_axi_bid),
   .s_axi_bready                 (bd_axi_bready),
   .s_axi_bresp                  (bd_axi_bresp),
   .s_axi_bvalid                 (bd_axi_bvalid),
   .s_axi_rdata                  (bd_axi_rdata),
   .s_axi_rid                    (bd_axi_rid),
   .s_axi_rlast                  (bd_axi_rlast),
   .s_axi_rready                 (bd_axi_rready),
   .s_axi_rresp                  (bd_axi_rresp),
   .s_axi_rvalid                 (bd_axi_rvalid),
   .s_axi_wdata                  (bd_axi_wdata),
   .s_axi_wlast                  (bd_axi_wlast),
   .s_axi_wready                 (bd_axi_wready),
   .s_axi_wstrb                  (bd_axi_wstrb),
   .s_axi_wvalid                 (bd_axi_wvalid),

   .uart_int                     (uart_int)
);


endmodule